Produkt mají v nabídce:
Design of Cost-Efficient Interconnect Processing Units - Coppola, Marcello (STMicroelectronics, Grenoble, France) a Grammatikakis, Miltos D. (ISD SA, Heraklion, Greece) a Locatelli, Riccardo (STMicroelectronics, Grenoble Cedex, France) a Maruccia, Giuseppe (STMicroelectronics, Grenoble, France) a Pieralisi, Lorenzo (ST
Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design.
