Produkt mají v nabídce:
Logic Synthesis and Verification Algorithms - Hachtel, Gary D. a Somenzi, Fabio
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).
